テーマ： Agentic AIの広がりと課題（仮題）

テクニカル・プログラム・コミッティーによって査読され採択された論文の発表です。

Presentation of papers reviewed and accepted by the Technical Program Committee.

各タイトルをクリックするとアブストラクトが確認できます / Click the title to explore the abstract information.

▼ CDC-RDC Verification Standard 1.0 for Interoperable Abstract Model

P CDC-RDC analysis has evolved as an inevitable stage in RTL quality signoff in the last two decades. Over this period, the designs have grown exponentially to SOC’s having 2 trillion+ transistors and chiplet’s having 7+ SOC’s. Today CDC-RDC verification has become a multifaceted effort across the chips designed for clients, servers, mobile, automotives, memory, AI/ML, FPGA etc. with focus on cleaning up of thousands of clocks and constraints, integrating the SVA’s for constraints in validation environment to check for correctness, looking for power domain and DFT logic induced crossings, finally signing off with netlist CDC-RDC to unearth any glitches and corrupted synchronizers during synthesis.
As the design sizes increased in every generation, the EDA tools could not handle running flatly and the only way of handling design complexity was through hierarchical CDC-RDC analysis consuming abstracts. Also, hierarchical analysis helps to enable the analysis in parallel with teams across the globe. Even with all this significant progress in capabilities of EDA tools the major bottleneck in CDC-RDC analysis of complex SOC’s and Chiplets is consuming abstracts generated by different vendor tools. Different vendor tool abstracts are seen because of multiple IP vendors; even in-house teams might deliver abstracts generated with different vendors tools.
The Accellera CDC Working-Group aims to define a standard CDC-RDC IP-XACT/TCL model to be portable and reusable regardless of the involved verification tool.
As moving from monolithic designs to IP/SOC with IPs sourced from a small or select providers to sourcing IPs globally (to create differentiated products), the quality must be maintained as driving faster time-to-market. In areas where the standards (SystemVerilog, OVM/UVM, LP/UPF…) are present, the integration is able to meet the above (quality, speed). However, in areas where standards (in this case, CDC-RDC) are not yet available, most options trade off either quality, or time-to-market, or both. Creating a standard for inter-operable collateral addresses this gap.
This tutorial aims to review CDC-RDC Basic Concepts and constraints, as well as the description of the reference verification flow, and addressing the goals, scope, structure & deliverables of the Accellera CDC Working Group which continuously maintains and enhances the specification of the standard abstract model.

講演：
Jean-Christophe Brignone
Accellera CDC Training Working Group chair

▼ Experimental Custom LSI Design and Evaluation with Open-Source EDA and PDK

Open-source HDL-to-GDSII flow software, including OpenROAD and OpenLANE, discovers progressive and easy design of digital logics. The Open-source EDA software significantly reduces costs of LSI development. Additionally, open-source PDKs are developed, and multi-project wafer semiconductor manufacturing services are provided that support the open-source PDKs. The open-source EDA, PDK and shuttle services reduce significantly cost barrier of LSI prototyping and development. However, there is still technical difficulty for constructing EDA toolchain environments and developing LSIs and still requires a comprehensive knowledge of both software and hardware. In order to improve the technical issues, we have constructed HDL-to-GDSII flow environment and develop an LSI by using open-source EDA software and Efabless shuttle service. And then we documented procedures for building and using open-source-based LSI development environments. In this presentation, we report a case study constructing open-source HDL-to-GDSII flow environment and evaluating the manufactured LSI by using open-source EDA and PDK. Furthermore, we tested an alternative open-source EDA flow for future chip manufacturing of ChipFoundry shuttle service.


講演：産業技術総合研究所 先端半導体研究センター
小笠原 泰弘