The Design & Verification Conference (DVCon) is the premier conference on the application of languages, tools, methodologies, and standards for the design and verification of electronic systems and integrated circuits. 

This highly technical conference focuses on the practical aspects of design and verification techniques and the use of standards in leading-edge projects, with the goal of facilitating the improvement and maturation of design and verification techniques throughout the industry by encouraging attendees to adopt and reference similar techniques in their own development flow. 

The DVCon Japan Steering Committee invites submissions of papers and presentations on practical experiences and novel applications of standards in various areas. Submissions on topics in the following areas are encouraged, but not limited to: 

Recommended Topics Area

■ Verification and Validation

• Advanced methodologies and test-benches
• Verification processes, regressions and resource management
• Debug and analysis of complex designs
• Multi-language design and verification
• Hardware/Software co-design and co-verification of embedded systems

■ Design and Verification Reuse / Automation

• Bridging verification and validation across multiple engines SoC and IP integration methods and tools
• Applications of the Accellera Portable Stimulus Standard
• Configuration management of IP and abstraction levels
• Interoperability of models and/or tools
• High-level synthesis from ESL languages
• Bridging virtual prototyping, simulation, emulation and/or FPGA prototyping

■ AI / ML and Big Data

• Automating the Optimization of Verification / Implementation Processes
• Coverage metrics and data analysis
• Performance modeling and/or analysis

■ Low-Power Design and Verification

• Low-power design and verification
• Clock domain crossing verification
• Power modeling, estimation and management

■ Safety-Critical / Security-Critical Design and Verification

• Verification and DO-254 compliance
• Automotive ISO 26262 Design and Verification Challenges
• Medical or Industrial Verification Challenges
• Requirements-Driven Verification Methodologies
• IP protection and security

■ Mixed-Signal Design and Verification

• Mixed-signal design & verification techniques
• Real-value modeling approaches
• Application of mixed-signal extensions for UVM

Submission Guidelines

DVCon Japan has adopted the following process to reduce the amount of time and effort required to prepare for the submission of papers.

• We accept submissions in the form of a paper (short paper, 2-6 pages) or slides (6 pages slides plus 100-words abstract)
• If you are accepted through peer review by the Technical Program Committee, please complete the paper and presentation slides (however, if you submit by slides, you do not need to complete the paper)
• Both formats are available in Japanese and English
• Submitted papers and slides will be reviewed by the Technical Program Committee under the DVCon Steering Committee and will be considered for presentation at the DVCon
• Presentation time at the conference will be 30 minutes, including Q&A
• As with other regional DVCons, corporate logos may only be included on the title slide of the presentation
• Please use the templates provided for both papers and slides

Timeline

Should you have any questions, please ask us using "Contact us" form.

Paper Template

There are 2 ways for paper submission, one is by short paper, the other is by 6pages slides + ~100 words abstract. Either way, please use the following template.

• For short paper submission, please download this template
• For paper submission by slides and abstract, please download this template

Paper Submission Site

Should you have your paper complete, make sure you use the DVCon Japan 2024 template, please submit the paper through the submission site.