The Design & Verification Conference (DVCon) is the premier conference on the application of languages, tools, methodologies, and standards for the design and verification of electronic systems and integrated circuits.
This highly technical conference focuses on the practical aspects of design and verification techniques and the use of standards in leading-edge projects, with the goal of facilitating the improvement and maturation of design and verification techniques throughout the industry by encouraging attendees to adopt and reference similar techniques in their own development flow.
The DVCon Japan Steering Committee invites submissions of papers and presentations on practical experiences and novel applications of standards in various areas. Submissions on topics in the following areas are encouraged, but not limited to:
Recommended Topics Area
■ Verification and Validation
■ Design and Verification Reuse / Automation
■ Machine Learning and Big Data
■ Low-Power Design and Verification
■ Safety-Critical / Security-Critical Design and Verification
■ Mixed-Signal Design and Verification
DVCon Japan has adopted the following process to reduce the amount of time and effort required to prepare for the submission of papers.
February 20, 2023 --- Short paper / 6pages slides + 100 words abstract submission due
April 24, 2023 --- Notify contributors of acceptance or rejection with the comments
May 22, 2023 --- Final Paper submission / Final presentation slides due
May 22, 2023 --- Final speaker fixed, and copyright form due
June 22, 2023 --- DVCon Japan 2023
Should you have any questions please contact us from Contact Us page.
Should you have your paper complete, make sure you use the DVCon Japan 2023 template, please submit the paper through the submission site.